`include "../../src/Memory.v"
`timescale 1ps/1ps


module MemoryTest;
    reg[31:0] address, writeData;
    reg MemRead, MemWrite;
    reg clk, reset;
    wire[31:0] readData;

    initial clk = 1;
    always #5 clk = ~clk;

    Memory U0(clk, reset, address, writeData, MemRead, MemWrite, readData);

    //内存初始化
    initial
    begin
        $readmemh("./romtable.dat", U0.units);
    end


    initial
    begin

        // #10
        // address = 32'd0;
        // writeData = 32'd12;
        // MemRead = 0;
        // MemWrite = 1;

        // #10 
        // address = 32'd4;
        // writeData = 32'd23;
        // MemRead = 0;
        // MemWrite = 1;

        #10
        address = 32'd0;
        MemRead = 1;
        MemWrite = 0;

        #10
        address = 32'd4;
        MemRead = 1;
        MemWrite = 0;

        #10
        $stop;

    end

    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;
    end


endmodule